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general description the max19700 is an ultra-low-power, mixed-signal ana- log front-end (afe) designed for td-scdma handsets and data cards. optimized for high dynamic perfor- mance at ultra-low power, the max19700 integrates a dual 10-bit, 7.5msps receive (rx) adc, dual 10-bit, 7.5msps transmit (tx) dac with td-scdma baseband filters, and three fast-settling 12-bit aux-dac channels for ancillary rf front-end control. the typical operating power in tx-rx fast mode is 36.3mw at a 5.12msps clock frequency. the rx adcs feature 54.9db sinad and 78dbc sfdr at a 1.87mhz input frequency with a 7.5msps sample frequency. the analog i/q input amplifiers are fully dif- ferential and accept 1.024v p-p full-scale signals. typical i/q channel matching is ?.22 phase and ?.02db gain. the tx dacs with td-scdma lowpass filters feature -3db cutoff frequency of 1.27mhz and >55db stop- band rejection at f image = 4.32mhz. the analog i/q full-scale output voltage range is selectable at ?10mv or ?00mv. the output common-mode voltage is selec- table from 0.9v to 1.4v and the i/q channel offset is adjustable. the typical i/q channel matching is ?.05db gain and ?.16 phase. the rx adc and tx dac share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (tdd) applications. a 3-wire serial interface controls power-management modes and the aux-dac channels. the max19700 operates on a single +2.7v to +3.3v analog supply and +1.8v to +3.3v digital i/o supply. the max19700 is specified for the extended (-40? to +85?) temperature range and is available in a 48-pin, thin qfn package. applications td-scdma handsets td-scdma data cards portable communication equipment features ? dual 10-bit rx adc and dual 10-bit tx dac ? ultra-low power 36.3mw at f clk = 5.12msps, fast mode 19.8mw at f clk = 5.12msps, slow mode low standby and shutdown current ? integrated td-scdma filters with >55db stopband rejection ? excellent dynamic performance sinad = 54.9db at f in = 1.87mhz (rx adc) sfdr = 76.5dbc at f out = 620khz (tx dac) ? excellent gain/phase match ?.22 phase, ?.02db gain (rx adc) at f in = 1.87mhz at -0.5dbfs ? three 12-bit, 1? aux-dacs ? single-supply operation ? multiplexed parallel digital i/o ? serial-interface control ? versatile power-control circuits shutdown, standby, idle, tx-rx disable ? miniature 48-pin thin qfn package (7mm x 7mm x 0.8mm) max19700 7.5msps, ultra-low-power analog front-end ________________________________________________________________ maxim integrated products 1 19-3549; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part* pin-package pkg code max19700etm 48 thin qfn-ep** t4877-4 max19700etm+ 48 thin qfn-ep** t4877-4 * all devices are specified over the -40? to +85? operating range. ** ep = exposed paddle. + denotes lead-free package. functional diagram appears at end of data sheet. dac3 n.c. v dd gnd sclk din t/r shdn dr v dd cs n.c. iap ian gnd clk gnd v dd qan gnd exposed paddle (gnd) qap v dd v dd refp 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d4 d5 ognd d6 d9 d8 d7 d3 d2 d1 d0 com refin qdp qdn v dd gnd idp idn v dd dac2 dac1 refn thin qfn max19700 ov dd top view 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 pin configuration
max19700 7.5msps, ultra-low-power analog front-end 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd, ov dd to ognd ..............................-0.3v to +3.4v gnd to ognd.......................................................-0.3v to +0.3v iap, ian, qap, qan, idp, idn, qdp, qdn, refp, refn, refin, com, dac1, dac2, dac3 to gnd .................-0.3v to (v dd + 0.3v) d0?9, dr, t/ r , shdn , sclk, din, cs , clk to ognd .....................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 48-pin thin qfn (derate 26.3mw/? above +70?) .......2.1w thermal resistance ja ..................................................38?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage v dd 2.7 3.0 3.3 v output supply voltage ov dd 1.8 v dd v ext1-tx, ext3-tx, and spi2-tx states; transmit dac operating mode (tx), f clk = 5.12mhz, f out = 620khz on both channels; aux-dacs on and at midscale 10.3 ext2-tx, ext4-tx, and spi4-tx states; transmit dac operating mode (tx), f clk = 5.12mhz, f out = 620khz on both channels; aux-dacs on and at midscale 12.4 ext1-rx, ext4-rx, and spi3-rx states; receive adc operating mode (rx), f clk = 5.12mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale 12.1 ext2-rx, ext3-rx, and spi1-rx modes; receive adc operating mode (rx), f clk = 5.12mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale 6.6 ext2-tx, ext4-tx, and spi4-tx modes; transmit dac operating mode (tx), f clk = 7.5mhz, f out = 620khz on both channels; aux-dacs on and at midscale 13.1 16 v dd supply current ext1-tx, ext3-tx, and spi2-tx modes; transmit dac operating mode (tx), f clk = 7.5mhz, f out = 620khz on both channels; aux-dacs on and at midscale 10.4 ma
max19700 7.5msps, ultra-low-power analog front-end _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units ext1-rx, ext4-rx, and spi3-rx modes; receive adc operating mode (rx), f clk = 7.5mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale 12.8 16 ext2-rx, ext3-rx, and spi1-rx modes; receive adc operating mode (rx), f clk = 7.5mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale 7 standby mode, clk = 0 or ov dd ; aux-dacs on and at midscale 2.7 4 idle mode, f clk = 7.5mhz; aux-dacs on and at midscale 4.7 6 ma v dd supply current shutdown mode, clk = 0 or ov dd 0.7 ? ext1-rx, ext2-rx, ext3-rx, ext4-rx, spi1-rx, spi3-rx modes; receive adc operating mode (rx), f clk = 7.5mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale 1.38 ma ext1-tx, ext2-tx, ext3-tx, ext4-tx, spi2-tx, spi4-tx modes; transmit dac operating mode (tx), f clk = 7.5mhz, f out = 620khz; aux-dacs on and at midscale 72.9 idle mode, f clk = 7.5mhz; aux-dacs on and at midscale 10.9 shutdown mode, clk = 0 or ov dd 0.01 ov dd supply current standby mode, clk = 0 or ov dd ; aux-dacs on and at midscale 0.03 ? rx adc dc accuracy resolution 10 bits integral nonlinearity inl ?.85 lsb differential nonlinearity dnl ?.55 lsb offset error residual dc offset error ?.5 ? %fs gain error include reference error ?.1 ? %fs dc gain matching ?.01 ?.25 db offset matching ?.5 lsb gain temperature coefficient ?5.7 ppm/? offset error (v dd ?%) ?.2 lsb power-supply rejection psrr gain error (v dd ?%) ?.04 %fs
max19700 7.5msps, ultra-low-power analog front-end 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units rx adc analog input input differential range v id differential or single-ended inputs ?.512 v input common-mode voltage range v cm v dd / 2 v r in switched capacitor load 720 k ? input impedance c in 5pf rx adc conversion rate maximum clock frequency f clk (note 2) 7.5 mhz channel i 5 data latency (figure 3) channel q 5.5 clock cycles rx adc dynamic characteristics (note 3) f in = 1.875mhz, f clk = 7.5mhz 53.7 55 signal-to-noise ratio snr f in = 3.5mhz, f clk = 7.5mhz 54.8 db f in = 1.875mhz, f clk = 7.5mhz 53.6 54.9 signal-to-noise plus distortion sinad f in = 3.5mhz, f clk = 7.5mhz 54.7 db f in = 1.875mhz, f clk = 7.5mhz 66 78 spurious-free dynamic range sfdr f in = 3.5mhz, f clk = 7.5mhz 70.1 dbc f in = 1.875mhz, f clk = 7.5mhz -84 third-harmonic distortion hd3 f in = 3.5mhz, f clk = 7.5mhz -72.1 dbc intermodulation distortion imd f 1 = 1.8 mhz, -7dbfs; f 2 = 1mhz, -7dbfs -75.6 dbc third-order intermodulation distortion im3 f 1 = 1.8mhz, -7dbfs; f 2 = 1mhz, -7dbfs -78 dbc f in = 1.875mhz, f clk = 7.5mhz -77.9 -64 total harmonic distortion thd f in = 3.5mhz, f clk = 7.5mhz -71 dbc aperture delay 3.5 ns overdrive recovery time 1.5x full-scale input 2 ns rx adc interchannel characteristics crosstalk rejection f in x ,y = 1.875m h z at - 0.5d bfs , f in x ,y = 1m h z at - 0.5d bfs ( n ote 4) -85 db amplitude matching f in = 1.875mhz at -0.5dbfs (note 5) ?.02 db phase matching f in = 1.875mhz at -0.5dbfs (note 5) ?.22 d eg r ees
max19700 7.5msps, ultra-low-power analog front-end _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units tx dac dc accuracy resolution n 10 bits integral nonlinearity inl ?.45 lsb differential nonlinearity dnl guaranteed monotonic (note 6) ?.26 lsb t a > +25? -4 1 +4 residual dc offset v os t a < +25? -6.5 ? +6.5 mv full-scale gain error incl ud e r efer ence er r or ( p eak- to- p eak er r or ) -50 +50 mv transmit-path dynamic performance corner frequency 3db corner 1.1 1.27 1.5 mhz passband ripple dc to 640khz (note 6) 0.28 0.5 db p-p group delay variation in passband dc to 640khz, guaranteed by design 50 100 ns error-vector magnitude evm dc to 700khz 2 % stopband rejection f image = 4.32mhz, f out = 800khz, f clk = 5.12mhz 55 dbc 2mhz 20 4mhz 46.5 5mhz 54.7 10mhz 81 baseband attenuation spot relative to 100khz 20mhz 88 db dac conversion rate f clk (note 2) 7.5 mhz in-band noise density n d f out = 620khz, f clk = 5.12mhz, offset = 500khz -121.7 dbc/hz third-order intermodulation distortion im3 f 1 = 620khz, f 2 = 640khz 76 dbc glitch impulse 10 pv s spurious-free dynamic range to nyquist sfdr f clk = 7.5mhz, f out = 620khz 60 76.5 dbc total harmonic distortion to nyquist thd f clk = 7.5mhz, f out = 620khz -74.8 -59 db signal-to-noise ratio to nyquist snr f clk = 7.5mhz, f out = 620khz 57.1 db
max19700 7.5msps, ultra-low-power analog front-end 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units transmit-path interchannel characteristics i-to-q output isolation f outx,y = 500khz, f outx,y = 620khz 85 db gain mismatch between dac outputs measured at dc -0.3 ?.05 +0.3 db phase mismatch between dac outputs f out = 620khz, f clk = 7.5mhz ?.16 d eg r ees differential output impedance 800 ? transmit-path analog output bit e7 = 0 (default) ?10 full-scale output voltage (table 6) v fs bit e7 = 1 ?00 mv bits cm1 = 0, cm0 = 0 (default) 1.32 1.4 1.48 bits cm1 = 0, cm0 = 1 1.25 bits cm1 = 1, cm0 = 0 1.1 output common-mode voltage (table 8) bits cm1 = 1, cm0 = 1 0.9 v receive transmit-path interchannel characteristics receive transmit isolation adc f ini = f inq = 1.875mhz, dac f outi = f outq = 620khz, f clk = 7.5mhz 85 db auxiliary dacs (dac1, dac2, dac3) resolution (note 6) 12 bits integral nonlinearity inl ?.25 lsb differential nonlinearity dnl guaranteed monotonic over codes 100 to 4000 (note 6) ?.65 lsb gain error ge r l > 200k ? ? 0.1 v output-voltage high v oh r l > 200k ? ? settling time from 1/4 fs to 3/4 fs 1 s glitch impulse from 0 to fs transition 24 nv s rx adc-tx dac timing characteristics clk rise to channel-i output data valid t doi figure 3 (note 6) 6.9 10 ns clk fall to channel-q output data valid t doq figure 3 (note 6) 9.3 13 ns clk rise/fall to dr rise/fall time t dr figure 3 (note 6) 8.5 12 ns i-dac data to clk fall setup time t dsi figure 5 (note 6) 10 ns
max19700 7.5msps, ultra-low-power analog front-end _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units q-dac data to clk rise setup time t dsq figure 5 (note 6) 10 ns clk fall to i-dac data hold time t dhi figure 5 (note 6) 0 ns clk rise to q-dac data hold time t dhq figure 5 (note 6) 0 ns clk duty cycle 50 % clk duty-cycle variation ?5 % digital output rise/fall time 20% to 80% 2.3 ns serial-interface timing characteristics (figure 6, note 6) falling edge of cs to rising edge of first sclk time t css 10 ns din to sclk setup time t ds 10 ns din to sclk hold time t dh 0ns sclk pulse-width high t ch 25 ns sclk pulse-width low t cl 25 ns sclk period t cp 50 ns sclk to cs setup time t cs 10 ns cs high pulse width t csw 80 ns mode-recovery timing characteristics (figure 7) from shutdown to rx mode, adc settles to within 1db sinad 75 shutdown wake-up time t wake , sd from shutdown to tx mode, dac settles to within 10 lsb error 25 ? fr om i d l e to rx m od e w i th c lk p r esent d ur i ng i d l e, ad c settl es to w i thi n 1d b s in ad 7.3 idle wake-up time (with clk) t wake , st0 from idle to tx mode with clk present during idle, dac settles to 10 lsb error 5 ? from standby to rx mode, adc settles to within 1db sinad 7.3 standby wake-up time t wake , st1 from standby to tx mode, dac settles to 10 lsb error 25 ? enable time from tx to rx, (ext2- tx to ext2-rx, ext4-tx to ext4-rx, and spi4-tx to spi3-rx modes) t enable , rx adc settles to within 1db sinad 500 ns enable time from rx to tx, (ext1- rx to ext1-tx, ext4-rx to ext4-tx, and spi3-rx to spi4-tx modes) t enable , tx dac settles to within 10 lsb error 1 s
max19700 7.5msps, ultra-low-power analog front-end 8 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units enable time from tx to rx, (ext1- tx to ext1-rx, ext3-tx to ext3-rx, and spi2-tx to spi1-rx modes) t enable , rx adc settles to within 1db sinad 7.3 ? enable time from rx to tx, (ext2- rx to ext2-tx, ext3-rx to ext3-tx, and spi1-rx to spi2-tx modes) t enable , tx dac settles to within 10 lsb error 5 s internal reference (refin = v dd ; v refp , v refn , v com levels are generated internally) positive reference v refp - v com 0.256 v negative reference v refn - v com -0.256 v common-mode output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma differential reference output v ref v refp - v refn +0.490 +0.512 +0.534 v differential reference temperature coefficient reftc ?0 ppm/? buffered external reference (external refin = 1.024v applied; v refp , v refn , v com levels are generated internally) reference input voltage v refin 1.024 v differential reference output v diff v refp - v refn 0.512 v common-mode output voltage v com v dd / 2 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma refin input current -0.7 ? refin input resistance 500 k ? digital inputs (clk, sclk, din, cs , d0?9, t/ r , shdn ) input high threshold v inh d0?9, clk, sclk, din, cs , t/ r , shdn 0.7 x ov dd v input low threshold v inl d0?9, clk, sclk, din, cs , t/ r , shdn 0.3 x ov dd v input leakage di in d0?9, clk, sclk, din, cs , t/ r , shdn = ognd or ov dd -1 +1 ? input capacitance dc in 5pf
max19700 7.5msps, ultra-low-power analog front-end _______________________________________________________________________________________ 9 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz (50% duty cycle), adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?. typical values are at t a = +25?, unless otherwise noted. c l < 5pf on all aux-dac outputs.) (note 1) parameter symbol conditions min typ max units digital outputs (d0?9, dr) output-voltage low v ol i sink = 200? 0.2 x ov dd v output-voltage high v oh i source = 200? 0.8 x ov dd v tri-state leakage current i leak -1 +1 ? tri-state output capacitance c out 5pf note 1: specifications from t a = +25? to +85? are guaranteed by production tests. specifications from t a = +25? to -40? are guaranteed by design and characterization. note 2: the minimum clock frequency for the max19700 is 2mhz. note 3: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5dbfs referenced to the amplitude of the digital outputs. sinad and thd are calculated using hd2 through hd6. note 4: crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. ffts are performed on each channel. the parameter is specified as the power ratio of the first and second channel fft test tone. note 5: amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. note 6: guaranteed by design and characterization. typical operating characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) rx adc channel-ia fft plot max19700 toc01 frequency (mhz) amplitude (dbfs) 3.0 2.0 1.0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 3.5 2.5 1.5 0.5 f clk = 7.5mhz f ia = 2mhz a ia = -0.5dbfs 8192-point data record hd3 hd2 ia rx adc channel-qa fft plot max19700 toc02 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f clk = 7.5mhz f qa = 2mhz a qa = -0.5dbfs 8192-point data record hd3 hd2 3.0 2.0 1.0 0 3.5 2.5 1.5 0.5 qa rx adc channel-ia two-tone fft plot max19700 toc03 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f clk = 7.5mhz f 1 = 2.0mhz f 2 = 2.1mhz a ia = -7dbfs per tone 8192-point data record 3.0 2.0 1.0 0 3.5 2.5 1.5 0.5 f 1 f 2
max19700 7.5msps, ultra-low-power analog front-end 10 ______________________________________________________________________________________ rx adc channel-qa two-tone fft plot max19700 toc04 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f clk = 7.5mhz f 1 = 2.0mhz f 2 = 2.1mhz a qa = -7dbfs per tone 8192-point data record f 1 f 2 3.0 2.0 1.0 0 3.5 2.5 1.5 0.5 rx adc signal-to-noise ratio vs. analog input frequency max19700 toc05 analog input frequency (mhz) snr (db) 90 80 60 70 20 30 40 50 10 47 49 51 53 55 57 45 0 100 qa ia rx adc signal-to-noise and distortion ratio vs. analog input frequency max19700 toc06 analog input frequency (mhz) sinad (db) 90 80 60 70 20 30 40 50 10 47 49 51 53 55 57 45 0100 qa ia rx adc total harmonic distortion vs. analog input frequency max19700 toc07 analog input frequency (mhz) thd (db) 90 80 60 70 20 30 40 50 10 -78 -76 -74 -72 -70 -68 -66 -80 0100 rx adc spurious-free dynamic range vs. analog input frequency max19700 toc08 analog input frequency (mhz) sfdr (dbc) 90 80 60 70 20 30 40 50 10 67 69 71 73 75 77 79 65 0 100 ia qa rx adc signal-to-noise ratio vs. analog input amplitude max19700 toc09 analog input amplitude (dbfs) snr (db) -3 -8 -13 -18 10 20 30 40 50 60 0 -23 qa ia f in = 1.9980913mhz rx adc signal-to-noise and distortion ratio vs. analog input amplitude max19700 toc10 analog input amplitude (dbfs) sinad (db) -3 -8 -13 -18 10 20 30 40 50 60 0 -23 qa ia f in = 1.9980913mhz rx adc spurious-free dynamic range vs. analog input amplitude max19700 toc11 analog input amplitude (dbfs) sfdr (dbc) -3 -8 -13 -18 45 55 50 60 65 70 75 80 40 -23 qa ia f in = 1.9980913mhz rx adc signal-to-noise ratio vs. sampling rate max19700 toc12 sampling rate (mhz) snr (db) 7 6 5 4 3 53.2 53.4 53.6 53.8 54.0 54.2 54.4 54.6 54.8 55.0 53.0 2 qa ia f in = 1.9980913mhz typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 11 rx adc signal-to-noise and distortion ratio vs. sampling rate max19700 toc13 sampling rate (mhz) sinad (db) 7 6 5 4 3 53.2 53.4 53.6 53.8 54.0 54.2 54.4 54.6 54.8 55.0 53.0 2 qa ia f in = 1.9980913mhz rx adc spurious-free dynamic range vs. sampling rate max19700 toc14 sampling rate (mhz) sfdr (dbc) 7 6 5 4 3 65 70 75 80 85 60 2 qa ia f in = 1.9980913mhz rx adc signal-to-noise ratio vs. clock duty cycle max19700 toc15 clock duty cycle (%) snr (db) 60 55 50 45 40 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 56.5 57.0 52.0 35 65 qa ia f in = 1.9980913mhz rx adc signal-to-noise and distortion ratio vs. clock duty cycle max19700 toc16 clock duty cycle (%) sinad (db) 60 55 50 45 40 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 56.5 57.0 52.0 35 65 qa ia f in = 1.9980913mhz rx adc spurious-free dynamic range vs. clock duty cycle max19700 toc17 clock duty cycle (%) sfdr (dbc) 60 55 50 45 40 71 72 73 74 75 76 77 78 79 80 70 35 65 qa ia f in = 1.9980913mhz rx adc offset error vs. temperature max19700 toc18 temperature ( c) offset error (%fs) 80 60 40 20 0 -20 0.2 0.4 0.6 0.8 1.0 1.2 0 -40 rx adc gain error vs. temperature max19700 toc19 temperature ( c) gain error (%fs) 80 60 40 20 0 -20 0.1 0.3 0.5 0.7 0.9 1.0 0 -40 0.2 0.4 0.6 0.8 tx path spurious-free dynamic range vs. sampling rate max19700 toc20 sampling rate (mhz) sfdr (dbc) 7.0 6.5 5.5 6.0 3.5 4.0 4.5 5.0 3.0 68 69 70 71 72 73 74 75 76 77 67 2.5 7.5 f out = f clk / 10 tx path spurious-free dynamic range vs. output frequency max19700 toc21 output frequency (khz) sfdr (dbc) 700 600 300 400 500 71 72 73 74 75 76 77 78 70 200 800 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19700 7.5msps, ultra-low-power analog front-end 12 ______________________________________________________________________________________ tx path spurious-free dynamic range vs. output amplitude max19700 toc22 output amplitude (dbfs) sfdr (dbc) -5 -10 -15 -20 -25 35 40 45 50 55 60 65 70 75 80 30 -30 0 f out = 620khz tx path channel-id spectral plot max19700 toc23 frequency (mhz) amplitude (dbfs) 3.2 2.2 1.2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 f id = 620khz tx path channel-id spectral plot with image rejection max19700 toc24 frequency (mhz) amplitude (dbfs) 3.5 4.5 2.5 1.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.5 f id = 800khz, f clk = 5.12msps image rejection tx path channel-qd spectral plot max19700 toc25 frequency (mhz) amplitude (dbfs) 3.2 2.2 1.2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 f qd = 620khz tx path channel-id two-tone spectral plot max19700 toc26 frequency (mhz) amplitude (dbfs) 3.2 2.2 1.2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.2 f 1 = 600khz, f 2 = 800khz f 1 f 2 tx path channel-qd two-tone spectral plot max19700 toc27 frequency (mhz) amplitude (dbfs) 3.2 2.2 1.2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.2 f 1 = 600khz, f 2 = 800khz f 1 f 2 supply current vs. sampling rate max19700 toc28 sampling rate (mhz) supply current (ma) 7.0 6.5 3.0 3.5 4.0 5.0 5.5 4.5 6.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 11.0 2.5 7.5 i vdd ext4-rx mode rx adc integral nonlinearity max19700 toc29 digital output code inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 transmit filter frequency response max19700toc30 frequency (mhz) amplitude (db) 1 -60 -80 -40 -20 0 -100 0.1 10 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 13 tx path integral nonlinearity max19700 toc31 digital output code inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 01024 tx path differential nonlinearity max19700 toc32 digital output code dnl (lsb) 896 768 512 640 256 384 128 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 0 1024 reference output voltage vs. temperature max19700 toc33 temperature ( c) v refp - v refn (v) 80 60 40 20 0 -20 0.505 0.510 0.515 0.520 0.500 -40 transmit filter passband ripple max19700 toc34 frequency (mhz) amplitude (db) 1.2 0.9 0.6 0.3 -0.10 -0.04 0 -0.06 -0.12 -0.08 -0.02 0.02 0.04 -0.14 0 aux-dac integral nonlinearity max19700 toc35 digital input code inl (lsb) 3072 2048 1024 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 4096 aux-dac differential nonlinearity max19700 toc36 digital input code dnl (lsb) 3072 2048 1024 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -0.8 0 4096 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 7.5mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19700 7.5msps, ultra-low-power analog front-end 14 ______________________________________________________________________________________ pin name function 1 refp upper reference voltage. bypass with a 0.33? capacitor to gnd as close to refp as possible. 2, 8, 11, 31, 33, 39 43 v dd analog supply voltage. bypass v dd to gnd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 3 iap channel ia positive analog input. for single-ended operation, connect signal source to iap. 4 ian channel ia negative analog input. for single-ended operation, connect ian to com. 5, 7, 12, 32, 42 gnd analog ground. connect all gnd pins to ground plane. 6 clk conversion clock input. clock signal for both receive adcs and transmit dacs. 9 qan channel qa negative analog input. for single-ended operation, connect qan to com. 10 qap channel qa positive analog input. for single-ended operation, connect signal source to qap. 13?8, 21?4 d0?9 digital i/o. outputs for receive adc in rx mode. inputs for transmit dac in tx mode. d9 is the most significant bit (msb) and d0 is the least significant bit (lsb). 19 ognd output-driver ground 20 ov dd output-driver power supply. supply range from +1.8v to v dd to accommodate most logic levels. bypass ov dd to ognd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 25 shdn active-low shutdown input. apply logic-low to place the max19700 in shutdown. 26 dr data-ready indicator. this digital output indicates channel i data (dr = 1) or channel q data (dr = 0) is present on the output. 27 t/ r transmit- or receive-mode select input. t/ r logic-low input sets the device in receive mode. a logic-high input sets the device in transmit mode. 28 din 3-wire serial-interface data input. data is latched on the rising edge of the sclk. 29 sclk 3-wire serial-interface clock input 30 cs 3-wire serial-interface chip-select input. logic-low enables the serial interface. 34, 35 n.c. no connection 36 dac3 analog output for auxiliary dac3 37 dac2 analog output for auxiliary dac2 38 dac1 analog output for auxiliary dac1 (afc dac, v out = 1.1v during power-up) 40, 41 idn, idp dac channel-id differential voltage output 44, 45 qdn, qdp dac channel-qd differential voltage output 46 refin reference input. connect to v dd for internal reference. 47 com common-mode voltage i/o. bypass com to gnd with a 0.33? capacitor. 48 refn negative reference i/o. conversion range is ?v refp - v refn ). bypass refn to gnd with a 0.33? capacitor. ep exposed paddle. exposed paddle is internally connected to gnd. connect ep to the gnd plane. pin description spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. detailed description the max19700 integrates a dual 10-bit rx adc and a dual 10-bit tx dac with td-scdma baseband filters while providing ultra-low power and high dynamic per- formance at a 7.5msps conversion rate. the rx adc analog input amplifiers are fully differential and accept 1v p-p full-scale signals. the tx dac analog outputs are fully differential with ?10mv full-scale output, selec- table common-mode range and offset adjust. the max19700 includes a 3-wire serial interface to control operating modes and power management. the serial interface is spi and microwire compatible. the max19700 serial interface selects shutdown, idle, standby, transmit (tx), and receive (rx) modes.
max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 15 to operate the device in tdd applications, configure the max19700 for tx or rx mode with the 3-wire serial interface. the rx adc and tx dac share a common digital bus to reduce the digital i/o to a single 10-bit parallel multiplexed bus. dual 10-bit rx adc the adc uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel ia and 5.5 clock cycles for channel qa. the adc full-scale analog input range is ? ref with a v dd / 2 ?.2v common-mode input range. v ref is the difference between v refp and v refn . see the reference configurations section for details. input track-and-hold (t/h) circuits figure 1 displays a simplified diagram of the rx adc input track-and-hold (t/h) circuitry. both adc inputs (iap, qap, ian, and qan) can be driven either differ- entially or single-ended. match the impedance of iap figure 1. max19700 rx adc internal t/h circuits s3b s3a com s5b s5a qap qan s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a iap ian s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b max19700
max19700 7.5msps, ultra-low-power analog front-end 16 ______________________________________________________________________________________ and ian, as well as qap and qan, and set the input signal common-mode voltage within the adc range of v dd / 2 (?00mv) for optimum performance. adc system timing requirements figure 3 shows the relationship between the clock, ana- log inputs, dr indicator, and the resulting output data. channel i (chi) and channel q (chq) are sampled on the rising edge of the clock signal (clk) and the result- ing data is multiplexed at the d0?9 outputs. chi data is updated on the rising edge and chq data is updat- ed on the falling edge of the clk. the dr indicator fol- lows clk with a typical delay time of 8.5ns and remains high when chi data is updated and low when chq data is updated. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for chi and 5.5 clock cycles for chq. digital input/output data (d0?9) d0?9 are the rx adc digital logic outputs when the max19700 is in receive mode. this bus is shared with the tx dac digital logic inputs and operates in half- duplex mode. d0?9 are the tx dac digital logic inputs when the max19700 is in transmit mode. the logic level is set by ov dd from 1.8v to v dd . the digital output coding is offset binary (table 1). keep the capacitive load on the digital outputs d0?9 as low as possible (<15pf) to avoid large digital currents feeding back into the analog portion of the max19700 and degrading its dynamic performance. buffers on the dig- ital outputs isolate the outputs from heavy capacitive loads. adding 100 ? resistors in series with the digital outputs close to the max19700 will help improve adc performance. see the max19700evkit schematic for an example of the digital outputs driving a digital buffer through 100 ? series resistors. during shdn, idle, and stby states, the pins d0?9 are internally pulled up to prevent floating digital inputs. to ensure no current flows through d0?9 i/o, the external bus needs to be either tri-stated or pulled up to ov dd and should not be pulled to ground. dual 10-bit tx dac and transmit path the dual 10-bit digital-to-analog converters (tx dac) operate with clock speeds up to 7.5mhz. the tx dac digital inputs, d0?9, are multiplexed on a single 10-bit bus. the voltage reference determines the tx path full- scale output voltage. see the reference configurations section for details on setting the reference voltage. each tx path channel integrates a lowpass filter tuned to meet the td-scdma spectral mask requirements. the td-scdma filters are tuned for 1.27mhz cutoff frequen- cy and >55db image rejection at f image = 4.32mhz, f out = 800khz, and f clk = 5.12mhz. see figure 4 for an illustration of the filter frequency response. table 1. output codes vs. input voltage differential input voltage differential input (lsb) offset binary (d0?9) output decimal code v ref x 512/512 511 (+full scale ?1 lsb) 11 1111 1111 1023 v ref x 511/512 510 (+full scale ?2 lsb) 11 1111 1110 1022 v ref x 1/512 +1 10 0000 0001 513 v ref x 0/512 0 (bipolar zero) 10 0000 0000 512 -v ref x 1/512 -1 01 1111 1111 511 -v ref x 511/512 -511 (-full scale +1 lsb) 00 0000 0001 1 -v ref x 512/512 -512 (-full scale) 00 0000 0000 0 figure 2. adc transfer function input voltage (lsb) -1 -510 -509 1024 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+ 1 -511 +510 +512 +511 -512 +509 (com) (com) offset binary output code (lsb) 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0011 11 1111 1111 11 1111 1110 11 1111 1101 01 1111 1111 10 0000 0000 10 0000 0001
max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 17 buffer amplifiers follow the td-scdma filters. the amplifier outputs are biased at an adjustable common- mode dc level and designed to drive a differential input stage with input impedance 70k ? . this simplifies the analog interface between rf quadrature upconverters and the max19700. many rf upconverters require a 0.9v to 1.5v common-mode bias. the spi-controlled dc common-mode bias eliminates discrete level-setting resistors and code-generated level shifting while pre- serving the full dynamic range of each tx dac. table 2 shows the tx path output voltage vs. input codes. table 10 shows the selection of dc common-mode levels. the buffer amplifiers also feature a programmable full- scale output level of ?10mv or ?00mv and indepen- dent dc offset correction of each i/q channel. both features are configured through the spi interface. the dc offset correction is used to optimize sideband and carrier suppression in the tx signal path (see tables 8 and 9). figure 3. rx adc system timing diagram t doq t cl t ch t clk t doi t dr 5 clock-cycle latency (chi) 5.5 clock-cycle latency (chq) dr chq d0?9 d0q chi d1i chq d1q chi d2i chq d2q chi d3i chq d3q chi d4i chq d4q chi d5i chq d5q chi d6i chq d6q chi chq clk figure 4. td-scdma filter frequency response 0.8 channel edge 4.32 image 1.27 f c 5.12 f clk freq (mhz) not to scale tx path: sfdr = 76.5dbc thd = -74.8dbc sinad = 57.1db -49.3db -15db -3db 0db -55db (min) -57.1db occupied channel amplitude td-scdma filter response dac sin(x)/x response
max19700 7.5msps, ultra-low-power analog front-end 18 ______________________________________________________________________________________ tx dac timing figure 5 shows the relationship between the clock, input data, and analog outputs. data for the i-channel (id) is latched on the falling edge of the clock signal, and q- channel (qd) data is latched on the rising edge of the clock signal. both i and q outputs are simultaneously updated on the next rising edge of the clock signal. 3-wire serial interface and operation modes the 3-wire serial interface controls the max19700 oper- ation modes as well as the three 12-bit aux-dacs. upon power-up, program the max19700 to operate in the desired mode. use the 3-wire serial interface to pro- gram the device for shutdown, idle, standby, rx, tx, or aux-dac modes. a 16-bit data register sets the mode control. the 16-bit word is comprised of a3?0 control bits and d11?0 data bits. tables 4, 5, and 6 show the max19700 operating modes and spi commands. the serial interface remains active in all modes. table 2. tx path output voltage vs. input codes (internal reference mode v refdac = 1.024v, external reference mode v refdac = v refin ; v fs = 410mv for 820mv p-p full scale and v fs = 500mv for 1v p-p full scale) differential output voltage (v) offset binary (d0?9) input decimal code 11 1111 1111 1023 11 1111 1110 1022 10 0000 0001 513 10 0000 0000 512 01 1111 1111 511 00 0000 0001 1 00 0000 0000 0 v v fs refdac 1024 1023 1023 () v v fs refdac 1024 1021 1023 () v v fs refdac 1024 3 1023 () v v fs refdac 1024 1 1023 () v v fs refdac 1024 1 1023 () ? v v fs refdac 1024 1021 1023 () ? v v fs refdac 1024 1023 1023 () ? figure 5. tx dac system timing diagram t dsq t dsi q: n - 2 i: n - 1 d0?9 clk id qd q: n - 1 i: n q: n i: n + 1 n - 2 n - 1 n n - 2 n - 1 n t dhq t dhi
max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 19 spi register description the operating modes can be selected by programming the control bits, a3?0, in the register as shown in table 3. modifying a3?0 bits will select from enable-16, aux-dac1, aux-dac2, aux-dac3, ioffset, qoffset, and comsel modes. enable-16 is the default operat- ing mode. this mode allows for shutdown, idle, and standby states as well as switching between fast, slow, rx, and tx modes. table 4 shows the max19700 power-management modes. table 5 shows the t/ r pin-controlled external tx-rx switching modes. table 6 shows the spi-controlled tx-rx switching modes. in enable-16 mode, the aux-dacs have independent control bits e6, e5, and e4, and the tx-path full-scale output can be set with bit e7. table 7 shows the auxil- iary dac enable codes and table 8 shows the full- scale output selection. bits e11 and e10 are reserved and need to be programmed to logic-low. bits e9 and e8 are not used. modes aux-dac1, aux-dac2, and aux-dac3 select the aux-dac channels named dac1, dac2, and dac3 and hold the data inputs for each dac. bits _d11?d0 are the data inputs for each aux-dac and can be pro- grammed through spi. the max19700 also includes two 6-bit registers that can be programmed to correct the offsets for the tx-path i and q channels indepen- dently (see table 9). use the comsel mode to select the output common-mode voltage with bits cm1 and cm0 (see table 10). shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the max19700 and placing the rx adc digital outputs in tri-state mode. when the rx adc outputs transition from tri-state to active, the last converted word is placed on the digital outputs. the tx dac previously stored data is lost when coming out of shutdown mode. the wake-up time from shutdown mode is dominated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 75? to enter rx mode and 25? to enter tx mode. in idle mode, the reference and clock distribution cir- cuits are powered, but all other functions are off. the rx adc outputs are forced to tri-state. the wake-up time is 7.3? to enter rx mode and 5s to enter tx mode. when the rx adc outputs transition from tri- state to active, the last converted word is placed on the digital outputs. in standby mode, the reference is powered, but the rest of the device functions are off. the wake-up time from standby mode is 7.3? to enter rx mode and 25? to enter tx mode. when the rx adc outputs transition from tri-state to active, the last converted word is placed on the digital outputs. fast and slow rx and tx modes in addition to the external tx-rx control, the max19700 also features slow and fast modes for switching between rx and tx operation. in fast tx mode, the rx adc core is powered on but the adc core digital out- puts are tri-stated on the d0?9 bus; likewise, in fast rx mode the transmit path (dac core and tx filter) is powered on but the dac core digital inputs are tri-stat- ed on the d0?9 bus. the switching time between tx to rx or rx to tx is fast because the converters are on and do not have to recover from a power-down state. in fast mode, the switching time between rx to tx and tx to rx is 1?. however, power consumption is higher in this mode because both the tx and rx cores are always on. to prevent bus contention in these states, the rx adc output buffers are tri-stated during tx and the tx dac input bus is tri-stated during rx. in slow mode, the rx adc core is off during tx; like- wise the tx dac and filters are turned off during rx to yield lower power consumption in these modes. for example, the power in slow tx mode is 31.2mw. the power consumption during rx is 21mw compared to power consumption in fast mode of 38.4mw. however, the recovery time between states is increased. the switching time in slow mode between rx to tx is 5s and tx to rx is 7.3?. external t/ r r switching control vs. serial-interface control bit e3 in the enable-16 register determines whether the device tx-rx mode is controlled externally through the t/ r input (e3 = low) or through the spi command (e3 = high). by default, the max19700 is in the external tx-rx control mode. in the external control mode, use the t/ r input (pin 27) to switch between rx and tx modes. using the t/ r pin provides faster switching between rx and tx modes. to override the external tx- rx control, program the max19700 through the serial interface. during shdn, idle, or stby modes, the t/ r input is overridden. to restore external tx-rx control, program bit e3 low and exit the shdn, idle, or stby modes through the serial interface.
max19700 7.5msps, ultra-low-power analog front-end 20 ______________________________________________________________________________________ spi timing the serial digital interface is a standard 3-wire connec- tion compatible with spi/qspi/microwire/dsp inter- faces. set cs low to enable the serial data loading at din. following a cs high-to-low transition, data is shift- ed synchronously, most significant bit first, on the rising edge of the serial clock (sclk). after 16 bits are loaded into the serial input register, data is transferred to the latch when cs transitions high. cs must transition high for a minimum of 80ns before the next write sequence. the sclk can idle either high or low between transi- tions. figure 6 shows the detailed timing diagram of the 3-wire serial interface. mode-recovery timing figure 7 shows the mode-recovery timing diagram. t wake is the wakeup time when exiting shutdown, idle, or standby mode and entering rx or tx mode. t enable is the recovery time when switching between either rx or tx mode. t wake or t enable is the time for the rx adc to settle within 1db of specified sinad performance and tx dac settling to 10 lsb error. t wake and t enable times are measured after either the 16-bit serial com- mand is latched into the max19700 by a cs transition high (spi controlled) or a t/ r logic transition (external tx-rx control). in fast mode, the recovery time is 1s to switch between tx or rx modes. table 3. max19700 mode control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 register name (msb) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 enable-16 e11 = 0 reserved e10 = 0 reserved e7 e6 e5 e4 e3 e2 e1 e0 0 0 0 0 aux-dac1 1d11 1d10 1d9 1d8 1d7 1d6 1d5 1d4 1d3 1d2 1d1 1d0 0 0 0 1 aux-dac2 2d11 2d10 2d9 2d8 2d7 2d6 2d5 2d4 2d3 2d2 2d1 2d0 0 0 1 0 aux-dac3 3d11 3d10 3d9 3d8 3d7 3d6 3d5 3d4 3d3 3d2 3d1 3d0 0 0 1 1 ioffset io5 io4 io3 io2 io1 io0 0 1 0 0 qoffset qo5 qo4 qo3 qo2 qo1 qo0 0 1 0 1 comsel cm1 cm0 0 1 1 0 table 4. power-management modes address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 mode function (power management ) description comment x000 x shdn shutdown rx adc = off tx dac = off aux-dac = off ref = off device is in complete shutdown overrides t/ r pin x001 x idle idle rx adc = off tx dac = off aux-dac = last state clk = on ref = on fast turn-on time moderate idle power overrides t/ r pin 0000 x010 x stby standby rx adc = off tx dac = off aux-dac = last state clk = off ref = on slow turn-on time low standby power overrides t/ r pin qspi is a trademark of motorola, inc. x = don't care.
system clock input (clk) both the rx adc and tx dac share the clk input. the clk input accepts a cmos-compatible signal level set by ov dd from 1.8v to v dd . since the interstage con- version of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 21 table 5. external tx-rx control using t/ r pin (t/ r = 0 = rx mode, t/ r = 1 = tx mode) address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 state function rx to tx-tx to rx switching speed description comment 0 ext1-rx rx mode rx adc = on tx dac = on rx bus = enable moderate power fast rx to tx when t/ r transitions 0 to 1 0011 1 ext1-tx fast-slow tx mode rx adc = off tx dac = on tx bus = enable low power slow tx to rx when t/ r transitions 1 to 0 0 ext2-rx (default) rx mode rx adc = on tx dac = off rx bus = enable low power slow rx to tx when t/ r transitions 0 to 1 0100 1 ext2-tx slow-fast tx mode rx adc = on tx dac = on tx bus = enable moderate power fast tx to rx when t/ r transitions 1 to 0 0 ext3-rx rx mode rx adc = on tx dac = off rx bus = enable low power slow rx to tx when t/ r transitions 0 to 1 0101 1 ext3-tx slow-slow tx mode rx adc = off tx dac = on tx bus = enable low power slow tx to rx when t/ r transitions 1 to 0 0 ext4-rx rx mode rx adc = on tx dac = on rx bus = enable moderate power fast rx to tx when t/ r transitions 0 to 1 0000 0110 1 ext4-tx fast-fast tx mode rx adc = on tx dac = on tx bus = enable moderate power fast tx to rx when t/ r transitions 1 to 0
max19700 possible jitter. any significant clock jitter limits the snr performance of the on-chip rx adc as follows: where f in represents the analog input frequency and t aj is the time of the clock jitter. clock jitter is especially critical for undersampling applications. consider the clock input as an analog input and route away from any analog input or other digital signal lines. the max19700 clock input operates with a ov dd / 2 voltage threshold and accepts a 50% ?5% duty cycle. 12-bit, auxiliary control dacs the max19700 includes three 12-bit aux-dacs (dac1, dac2, dac3) with 1? settling time for controlling vari- able-gain amplifier (vga), automatic gain-control (agc), and automatic frequency-control (afc) func- tions. the aux-dac output range is 0.1v to 2.56v. during power-up, the vga and agc outputs (dac2 and dac3) are at zero. the afc dac (dac1) is at 1.1v during power-up. the aux-dacs can be independently log snr ft = ? ? ? ? ? ? 20 1 2 in aj 7.5msps, ultra-low-power analog front-end 22 ______________________________________________________________________________________ table 6. tx-rx control using spi commands address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 mode function (tx-rx switching speed) description comments 1011 x spi1-rx slow rx mode rx adc = on tx dac = off rx bus = enable low power slow rx to tx through spi command 1100 x spi2-tx slow tx mode rx adc = off tx dac = on tx bus = enable low power slow tx to rx through spi command 1101 x spi3-rx fast rx mode rx adc = on tx dac = on rx bus = enabled moderate power fast rx to tx through spi command 0000 1110 x spi4-tx fast tx mode rx adc = on tx dac = on tx bus = enabled moderate power fast tx to rx through spi command table 7. aux-dac enable table (enable-16 mode) e6 e5 e4 aux-dac3 aux-dac2 aux-dac1 000 on on on 001 on on off 010 on off on 011 on off off 100 off on on 101 off on off 110 off off on 111 off off off table 8. tx-path full-scale select (enable-16 mode) e7 tx-path output full scale 0 (default) 820mv p-p 11v p-p x = don't care.
controlled through the spi bus, except during shdn mode where the aux-dacs are turned off completely and the output voltage is set to zero. in stby and idle modes the aux-dacs maintain the last value. on wakeup from shdn, the aux-dacs resume the last values. loading on the aux-dac outputs should be carefully observed to achieve specified settling time and stabili- ty. the capacitive load must be kept to a maximum of 5pf including package and trace capacitance. the resistive load must be greater than 200k ? . if capacitive loading exceeds 5pf, then add a 10k ? resistor in series with the output. adding the series resistor helps drive larger load capacitance (<15pf) at the expense of slower settling time. reference configurations the max19700 features an internal precision 1.024v bandgap reference that is stable over the entire power- supply and temperature ranges. the refin input pro- vides two modes of reference operation. the voltage at refin (v refin ) sets the reference operation mode (table 11). in internal reference mode, connect refin to v dd . v ref is an internally generated 0.512v ?%. com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v ref / 2, and v refn = v dd / 2 - v ref / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in buffered external reference mode, apply 1.024v ?0% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v refin / 4, and v refn = v dd / 2 - v refin / 4. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 23 table 9. offset control bits for i and q channels (ioffset or qoffset mode) bits io5?o0 when in ioffset mode, bits qo5?o0 when in qoffset mode io5/qo5 io4/qo4 io3/qo3 io2/qo2 io1/qo1 io0/qo0 offset 1 lsb = (vfs p-p /1023) 1 1 1 1 1 1 -31 lsb 1 1 1 1 1 0 -30 lsb 1 1 1 1 0 1 -29 lsb 100010-2 lsb 100001-1 lsb 1000000mv 0 0 0 0 0 0 0mv (default) 0000011 lsb 0000102 lsb 01110129 lsb 01111030 lsb 01111131 lsb note: for transmit full-scale select of 820mv p-p : 1 lsb = (820mv p-p /1023) = 0.8016mv. for transmit full-scale select of 1v p-p : 1 lsb = (1v p-p /1023) = 0.9775mv. table 10. common-mode select (com- sel mode) cm1 cm0 tx-path output common mode (v) 0 0 1.4 (default) 0 1 1.25 1 0 1.1 1 1 0.9
max19700 capacitor. in this mode, the tx-path full-scale output is proportional to the external reference. for example, if the v refin is increased by 10% (max), the tx-path full- scale output is also increased by 10% or ?51mv. power-on reset the max19700 features a power-on-reset (por) func- tion that sets the device in a known state upon power- up. the default state is ext2-rx. the por circuit is designed to accommodate power supplies that ramp 7.5msps, ultra-low-power analog front-end 24 ______________________________________________________________________________________ figure 6. 3-wire serial-interface timing diagram msb cs sclk din lsb t csw t cs t cp t css t cl t ch t ds t dh figure 7. max19700 mode-recovery timing diagram sclk cs din d0-d9 id/qd t/r r x - > t x adc digital output. sinad settles within 1db dac analog output output settles to 10 lsb error 16-bit serial data input t enable , rx external t/r control t enable , tx external t/r control t wake, sd, st_ to tx mode or t enable , tx t wake, sd, st_ to rx mode or t enable , rx t/r t x - > r x
from 0v to v dd in less than or equal to 1ms. for power supplies that ramp from 0v to v dd in greater than 1ms, program the max19700 to enter the desired state using the spi interface. applications information using balun transformer ac-coupling an rf transformer (figure 8) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum adc performance. connecting the center tap of the transformer to com provides a v dd / 2 dc level shift to the input. a 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. in gener- al, the max19700 provides better sfdr and thd with fully differential input signals than single-ended signals, especially for high input frequencies. in differential mode, even-order harmonics are lower as both inputs (iap, ian, qap, qan) are balanced, and each of the rx adc inputs only requires half the signal swing com- pared to single-ended mode. figure 9 shows an rf transformer converting the max19700 tx dac differen- tial analog outputs to single-ended. using op-amp coupling drive the max19700 rx adc with op amps when a balun transformer is not available. figures 10 and 11 show the rx adc being driven by op amps for ac-cou- pled single-ended and dc-coupled differential applica- tions. amplifiers such as the max4454 and max4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. the op-amp circuit shown in figure 11 can also be used to interface with the tx dac differential analog outputs to provide gain or buffering. the tx dac differential ana- log outputs cannot be used in single-ended mode because of the internally generated common-mode level. also, the tx dac analog outputs are designed to drive a differential input stage with input impedance 70k ? . if single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conver- sion and select an amplifier with proper input common- mode voltage range. tdd mode the max19700 is optimized to operate in td-scdma applications. when fast mode is selected, the max19700 can switch between tx and rx modes through the t/ r pin in typically 1?. the rx adc and tx dac operate independently. the rx adc and tx dac digital bus are shared forming a single 10-bit parallel bus. using the 3-wire serial interface or external t/ r pin, select between rx mode to enable the rx adc or tx mode to enable the tx dac. when operating in rx mode, the tx dac bus is not enabled and in tx mode the rx adc bus is tri-stated eliminating any unwanted max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 25 table 11. reference modes v refin reference mode >0.8v x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33? capacitor. 1.024v ?0% buffered external reference mode. an external 1.024v ?0% reference voltage is applied to refin. v ref is internally generated to be v refin / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. figure 8. balun transformer-coupled single-ended-to- differential input drive for rx adc com iap ian 25 ? 0.1 f 0.33 f 25 ? 0.1 f v in max19700 22pf 22pf qap qan 25 ? 0.1 f 0.33 f 25 ? 0.1 f v in 22pf 22pf
max19700 spurious emissions and preventing bus contention. in tdd mode, the max19700 uses 38.4mw power in rx mode at f clk = 7.5mhz, and 39.3mw in tx mode. td-scdma application figure 12 illustrates a typical td-scdma application circuit. the max19700 is designed to interface directly with the max2507 and max2392 radio front-ends to provide a complete ?f-to-bits?front-end solution. the max19700 provides several features that allow direct interface to the max2392 and max2507: integrated tx filters reduce component count, lower cost, and meet td-scdma spectral mask requirements programmable dc common-mode tx output levels eliminate discrete dc level-shifting components while preserving tx dac full dynamic range optimized tx full-scale output level eliminates dis- crete amplifiers for i/q gain control tx-i/q offset correction eliminates discrete trim dacs for offset trim to improve sideband/carrier suppression one microsecond settling time aux-dacs for vga and agc control allow fast, accurate tx power and rx gain control grounding, bypassing, and board layout the max19700 requires high-speed board layout design techniques. refer to the max19700 ev kit data sheet for a board layout reference. place all bypass capacitors as close to the device as possible, prefer- ably on the same side of the board as the device, using surface-mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass ov dd to ognd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass refp, refn, and com each to gnd with a 0.33? ceramic capacitor. bypass refin to gnd with a 0.1? capacitor. multilayer boards with separated ground and power planes yield the highest level of signal integrity. use a split ground plane arranged to match the physical loca- tion of the analog ground (gnd) and the digital output driver ground (ognd) on the device package. connect the max19700 exposed backside paddle to gnd plane. join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. the ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. 7.5msps, ultra-low-power analog front-end 26 ______________________________________________________________________________________ figure 9. balun transformer-coupled differential-to-single- ended output drive for tx dac max19700 idp idn v out qdp qdn v out figure 10. single-ended drive for rx adc max19700 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf qap qan com iap ian 0.1 f r iso 50 ? r iso 50 ? refp refn v in 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in
make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system? ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensi- tive analog traces. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. dynamic parameter definitions adc and dac static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the device are measured using the best straight line fit (dac figure 13a). differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes (adc) and a monotonic transfer function (adc and dac) (dac figure 13b). adc offset error ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. dac offset error offset error (figure 13a) is the difference between the ideal and actual offset point. the offset point is the out- put value when the digital input is midscale. this error affects all codes by the same amount and usually can be compensated by trimming. max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 27 figure 11. rx adc dc-coupled differential drive max19700 iap com ian r iso 22 ? r iso 22 ? r11 600 ? r9 600 ? r3 600 ? r2 600 ? r1 600 ? r10 600 ? r8 600 ? r5 600 ? r4 600 ? r7 600 ? r6 600 ? c in 5pf c in 5pf
max19700 7.5msps, ultra-low-power analog front-end 28 ______________________________________________________________________________________ figure 12. typical application circuit for td-scdma radio rx adc 10-bit rx adc 10-bit tx dac 10-bit tx dac 10-bit adc output mux dac input mux clk 10-bit digital baseband processor serial bus max 19700 max2392 td-scdma zif receiver max2507 td-scdma direct modulator filter filter tcxo afc agc vga rf out aux-dac3 aux-dac1 aux-dac2 rf in v cc 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (0.5 lsb) at step 001 (0.25 lsb) 111 digital input code analog output value figure 13a. integral nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-0.25 lsb) differential linearity error (+0.25 lsb) 1 lsb 1 lsb digital input code analog output value figure 13b. differential nonlinearity
adc gain error ideally, the adc full-scale transition occurs at 1.5 lsb below full scale. the gain error is the amount of devia- tion between the measured transition point and the ideal transition point with the offset error removed. adc dynamic parameter definitions aperture jitter figure 14 shows the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 14). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error) and results directly from the adc? resolution (n bits): snr(max) = 6.02db x n + 1.76db (in db) in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 ? 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f 1 and f 2 , are present at the inputs. the intermodulation prod- ucts are (f 1 ? 2 ), (2 ? f 1 ), (2 ? f 2 ), (2 ? f 1 ? 2 ), (2 ? f 2 ? 1 ). the individual input tone levels are at -7dbfs. 3rd-order intermodulation (im3) im3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f 1 and f 2 , are present at the inputs. the 3rd-order intermodulation products are (2 x f 1 ? 2 ), (2 ? f 2 ? 1 ). the individual input tone levels are at - 7dbfs. power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ?%. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. note that the t/h performance is usually the limiting factor for the small-signal input bandwidth. thd (v +v +v +v +v ) v 2 2 3 2 4 2 5 2 6 2 1 = ? ? ? ? ? ? ? ? 20log max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 29 hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 14. t/h aperture timing
max19700 full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as the full- power bandwidth frequency. dac dynamic parameter definitions total harmonic distortion thd is the ratio of the rms sum of the output harmonics up to the nyquist frequency divided by the fundamental: where v 1 is the fundamental amplitude and v 2 through v n are the amplitudes of the 2nd through nth harmonic up to the nyquist frequency. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component up to the nyquist frequency excluding dc. thd (v + v + ...+ v ) v 2 2 3 2 n 2 1 = ? ? ? ? ? ? ? ? 20log 7.5msps, ultra-low-power analog front-end 30 ______________________________________________________________________________________ clk serial interface and system control iap ian qap qan idp idn qdp qdn refp refn com refin din sclk cs system clock offset program filter filter 1.024v reference buffer 10-bit adc 10-bit adc 10-bit dac half- duplex bus 10-bit dac 12-bit dac 12-bit dac 12-bit dac dac1 dac2 dac3 dr d0?9 shdn t/r max19700 functional diagram
max19700 7.5msps, ultra-low-power analog front-end ______________________________________________________________________________________ 31 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm 1 d rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor detail b e l l1 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max19700 7.5msps, ultra-low-power analog front-end maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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